一种容错可逆的通用移位寄存器设计

J4 ›› 2015, Vol. 32 ›› Issue (5): 600-606.

一种容错可逆的通用移位寄存器设计

杨洁汤其妹陈付龙齐学梅叶和平

1 安徽师范大学数学计算机科学学院，安徽芜湖 241003；
2 安徽师范大学网络与信息安全工程技术研究中心，安徽芜湖 241003

收稿日期:2014-12-01 修回日期:2015-03-18 出版日期:2015-09-28 发布日期:2015-09-28
通讯作者: 陈付龙（1978-）博士，副教授，主要研究方向为量子可逆计算、嵌入式计算。 E-mail:long005@mail.ahnu.edu.cn
作者简介:杨洁（1988-）研究生，主要研究方向量子可逆计算、嵌入式计算。E-mail:yangjie_7@126.com
基金资助:
国家自然科学基金项目(61370050)，安徽省自然科学基金项目(1308085QF118)，安徽省高校省级自然科学研究项目重点项目(KJ2014A084)，安徽师范大学创新基金项目(2013CXJJ01)资助

Design of Fault Tolerant Universal Shift Register Using Reversible Logic

YANG Jie, TANG Qimei, CHEN Fulong, QI Xuemei, YE Heping

1 School of Mathematics and Computer Science , Anhui Normal University, Wuhu 241003, China；
2 Network and Information Security Engineering Research Center, Anhui Normal University, Wuhu 241003, China

Received:2014-12-01 Revised:2015-03-18 Published:2015-09-28 Online:2015-09-28

摘要/Abstract

摘要：

为了使计算系统具有低功耗和容错能力，基于可逆逻辑设计了一种容错的通用移位寄存器。提出了一种新型的容错可逆逻辑门(Parity-Preserving D Flip_flop Gate, PP_DFG)，利用它和存在的容错门，完成了寄存器和多路数据选择器的设计。综合上述模块，构建了容错可逆的通用移位寄存器电路，用Verilog 硬件描述语言建模，仿真显示电路逻辑结构正确。同现有电路相比，根据量子代价、延迟和无用输出对其进行性能评估，结果表明该电路不仅具有容错功能，而且性能提高了16%~50%。设计的电路可作为一种重要的存储元件应用于未来的低功耗计算系统。

关键词: 可逆逻辑, 容错, PP_DFG门, 移位寄存器, 仿真

Abstract:

In order to make the computing system with low power consumption and fault- tolerant ability, a fault-tolerant universal shift register was designed using reversible logic. A new reversible fault-tolerant gate named Parity Preserving D Flip_flop Gate (PP_DFG) was proposed. Some circuits such as register and multiplexer were designed using PP_DFG and existing gates. Based on the above modules, the fault-tolerant reversible universal shift register was built. It was modeled in Verilog hardware description language for verification. Simulation results indicate its logic structure is correct. Compared with the existing ones in terms of quantum cost, delay and garbage outputs, the proposed circuit not only supports fault-tolerant but also has 16%~50% performance improvement. This circuit can be used as a kind of important storage element applied in future low-power computing system.

Key words: reversible logic, fault tolerant, parity preserving D Flip_flop gate, universal shift register, simulation

杨洁汤其妹陈付龙齐学梅叶和平. 一种容错可逆的通用移位寄存器设计[J]. J4, 2015, 32(5): 600-606.

YANG Jie, TANG Qimei, CHEN Fulong, QI Xuemei, YE Heping. Design of Fault Tolerant Universal Shift Register Using Reversible Logic[J]. J4, 2015, 32(5): 600-606.

参考文献

[1]Landauer R, Irreversibility and heat generation in the computational process [J.IBM J[J].Res.and Develop., 1961, 5(2):183-191 [2]Bennett C H, Logical reversibility of computation[J.IBM J[J].Res. Develop., 1973, 17(6):525-532 [3] Perkowsi M, Jozwiak L, Kerntopf P, Al-Rabadi A, Coppoa A, BullerSong AX, Khan MMHA, Yanushkevich S, Shmerko VS, Chzazowska-Jeske M.A general decomposition for reversible logic[C].Proc.RM, Starkville.,2001: 119-138. [4]Ren J, Semenov V K.Progress with physically and logically reversible superconducting digital circuits[J].IEEE Trans. Appl. Supercond, 2011, 21(3):780-786 [5]Taraphdara C, Chattopadhyay T, Roy J.Machzehnder interferometer-based all-optical reversible logic gate[J].Opt. Laser Technol., 2010, 42(2):249-259 [6]Ma X, Huang J, Metra C, et al.Detecting multiple faultsin one-dimensional arrays of reversible QCA gates[J].J. Electron. Test., 2009, 25(1):39-54 [7]Lü Hongjun, Peng Fei, Wu Tianhao, et al.Irreversible logic operation accomplished by quantum reversible logic circuits[J].量子电子学报, 2009, 26(6):668-674 [8]Nielsen MA, Chuang I.Quantum computation and quantuminformation[J].Am. J. Phy., 2002, 70(5):558-559 [9] Merkle R C.Two types of mechanical reversible logic [J].Nanotechnology, 1993, 4(2):114-131 [10] Toffoli T.Reversible computing [J].MIT Lab. Comput. Sci., Cambridge, MA, USA, Tech. Rep. MIT/LCS/TM-151, 1980, 85(1):632-644 [11]Md.Selim AL Mamum and BK.Karmaker. Design of Reversible Counter[J].Int. J. Adv.Comp.r Sci. Appl., 2014, 5(10):124-128 [12]MohammadiM, EshghiM.On figures of merit in reversible and quantum logic designs[C].Quant.Info.Proc., 2009, 8(4):297-318. [13]Qi Xuemei, ChenFulong, LuoYonglong.Efficient fault tolerant reversible Hamming code encoding and detection circuits[J].量子电子学报, 2013, 30(5):586-593 [14]Parhami B.Fault tolerant reversible circuits[C]. Proc. ACSSC., 2006, 1726-1729. [15]ThapliyalH, Vinod A P.Design of reversible sequential elements with feasibility of transistor implementation[C].Proc. the 2007 IEEE Intl. Symp. On Cir.and Sys., 2007, 625–628. [16] Biswas A K, Jamal L, Mottalib1M A et al.Design of a Reversible Parallel Loading Shift Register[J].Dhaka Univ. J.Eng& Tech., 2011, 1(2):1-5 [17] Krishnaveni D, Priya MG.A Novel Design of Reversible Universal Shift Register with Reduced Delay and Quantum Cost[J].J.Comput., 2012, 4(2):164-173 [18]Al Mamun M S, Mandal I, Hasanuzzaman M.Design of Universal Shift Register Using Reversible Logic[J].Int. J. Eng.&Tech., 2012, 2(9):1620-1625 [19]Qi Xuemei, ChenFulong, Wang Hongtao, Sun Yunxiang, Guo Liangmin.Novel Parity-Preserving Designs of Reversible 4-Bit Comparator [J].Int. J. Theor. Phys., 2014, 53(4):1092-1102 [20] Fredkin E, Toffoli T.Conservative logic[J].Int. J. Theor. Phys., 1982, 21(1):219-253