[1]Rice J. (2013).. An overview of fault models and testing approaches for reversible logic[J].Communications, Computers and Signal Processing PACRIM,2013,:-
[2] Patel, K. N., J. P. Hayes, et al. (2004). "Fault testing for reversible circuits." Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 23(8): 1220-1230
[3]Sen.[J].B., J. Das, et al. (2012). A DFT methodology targeting online testing of reversible circuit. Devices, Circuits and Systems (ICDCS,2012,:-
[4] Biamonte, J. (2005). ATPG for reversible circuits using technology? related fault models. Proc. 7th International Symposium on Representations and Methodology of Future Computing Technologies
[5]Hayes.[J].J. P., I. Polian, et al. (2004). Testing for missing-gate faults in reversible circuits. Test Symposium,2004,:-
[6]Zhong.[J].J. and J. C. Muzio (2006). Analyzing fault models for reversible logic circuits. Evolutionary Computation,2006,:-
[7] Ramasamy, K., R. Tagare, et al. (2004). Fault localization in reversible circuits is easier than for classical circuits. Proceedings of the International Workshop on Logic and Synthesis, June 2004
[8] Barenco, A., C. H. Bennett, et al. (1995). "Elementary gates for quantum computation." Physical Review A 52(5): 3457
[9] Wille, R., A. Lye, et al. (2013). "Considering nearest neighbor constraints of quantum circuits at the reversible circuit level." Quantum Information Processing: 1-15
[10] Sasanian, Z., R. Wille, et al. (2012). Realizing reversible circuits using a new class of quantum gates. Proceedings of the 49th Annual Design Automation Conference, ACM
[11] Maslov D. Reversible logic synthesis benchmarks page [OL].[2014-04-20].http://webhome. cs.uvic.ca/ ~dmaslov