一种长周期和大倍频系数条件下的数字锁相环

量子电子学报

一种长周期和大倍频系数条件下的数字锁相环

田禹泽1,2，王煜2，*，赵欣2，黄书华2，常振2，邱晓晗2

1中国科学技术大学环境科学与光电技术学院，安徽省合肥市 230027； 2中国科学院安徽光学精密机械研究所环境光学与技术重点实验室，安徽省合肥市 230031

出版日期:2019-03-28 发布日期:2019-03-20
通讯作者: 王煜E-mail：yuwang@aiofm.ac.cn。
作者简介:田禹泽（1989-），辽宁鞍山人，博士研究生，研究方向为星载设备时钟源开发，E-mail：yztian@aiofm.ac.cn。
基金资助:
Supported by National Natural Science Foundation of China（国家自然科学基金，41676184）；National Key Research and Development Plan（国家重点研发计划，2016YFC0200400）

A digital phase-locked loop for long period input signals and large frequency multiplication coefficient

TIAN Yuze1,2, WANG Yu2, ZHAO Xin2, HUANG Shuhua2, CHANG Zheng2, QIU Xiaohan2

1 School of Environmental Science and Optoelectronic Technology, University of Science and Technology, Hefei 230027, China 2 Key Laboratory of Environment Optics and Technology, Anhui Institute of Optics and Fine Mechanics, Chinese Academy of Science, Hefei 230031, China

Published:2019-03-28 Online:2019-03-20

摘要/Abstract

摘要： 遥感设备需要配备高精度的本地时钟源与卫星平台时钟同步，数字锁相环设计是时钟同步和倍频的关键技术，而长周期输入信号和大倍频系数从两方面增加了设计难度。该文设计了一种针对秒脉冲同步和10000倍倍频条件下的数字锁相环，通过建立Z域模型和S域近似分析了其响应特性，用现场可编程门阵列予以实现。实验表明，本设计实现的数字锁相环最短可以在5个输入时钟周期内进入锁定状态，稳定工作时每秒累积误差小于0.1ms，在实际应用中可以稳定输出本地时钟，满足遥感设备时钟同步和倍频的需求。

关键词: 遥感, DPLL, 倍频, 反馈控制, FPGA

Abstract: The remote sensing equipment needs to be equipped with a high precision local clock source in order to synchronize with the clock of the satellite platform. The digital phase locked-loop design is a key technology of synchronization and frequency multiplication of the clock. Long period input signals and large frequency multiplication coefficient add more difficulties of the loop design from two different ways. Under the condition of second pulse synchronization and 10000 times frequency doubling, a method of digital loop parameter algorithm was proposed. The response characteristics of the loop were analyzed by establishing the Z domain model and the approximate S domain model. The whole design was implemented by field programmable gate array. Experiments show that the design of the digital phase-locked loop can be locked in 5 input clock cycles, and the cumulative error is less than 0.1 millisecond per second during stable operation. In practical application, the digital phase locked loop can stabilize the output of the local clock to meet the needs of the remote sensing devices' clock synchronization and frequency multiplication.

Key words: remote sensing, digital phase-locked loop, frequency multiplication, feedback control, field programmable gate array

田禹泽1,2，王煜2，*，赵欣2，黄书华2，常振2，邱晓晗2. 一种长周期和大倍频系数条件下的数字锁相环[J]. 量子电子学报.

TIAN Yuze1,2, WANG Yu2, ZHAO Xin2, HUANG Shuhua2, CHANG Zheng2, QIU Xiaohan2. A digital phase-locked loop for long period input signals and large frequency multiplication coefficient[J]. Chinese Journal of Quantum Electronics.

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