四元量子可逆半加器、全加器和并行加法器电路的设计

doi:10.3969/j.issn.1007-5461.2023.05.015

摘要/Abstract

摘要： 多元量子逻辑比二元量子逻辑具有更多的优点, 是量子计算技术中一个重要的研究领域, 而加法器电路和减法器电路是计算机和其他复杂计算系统中各种计算单元的主要组成部分。提出了一种四元量子可逆半加器电路, 该电路由四元1-qudit 门、2-qudit Feynman 门和Muthukrishnan-Stroud 门构成, 以及一种四元量子可逆全加器和四元量子并行加法器电路, 并将所提出设计与现有电路进行了比较, 优化了其性能。

关键词: 量子信息, 可逆逻辑, 四元逻辑, 量子可逆加法器电路

Abstract: Multiple valued quantum logic has more advantages than binary quantum logic and is a promising research area in quantum computing technology. Adder circuits, as well as subtractor circuits, are the major components of various computational units in computers and other complex computational systems. A quaternary quantum reversible half-adder circuit is put forward, which consists of quaternary 1-qudit gates, 2-qudit Feynman gates and Muthukrishnan-Stroud gates, as well as a quaternary quantum reversible full adder and a quaternary quantum parallel adder circuit. The proposed designs are compared with the existing designs and the improvements on the performance of the proposed circuits are reported.

Key words: quantum information, reversible logic, quaternary logic, quantum reversible adder circuits

中图分类号:

TN91

汤其妹. 四元量子可逆半加器、全加器和并行加法器电路的设计[J]. 量子电子学报, 2023, 40(5): 759-769.

TANG Qimei. Design of quaternary quantum reversible half⁃adder, full⁃adder and parallel adder circuits[J]. Chinese Journal of Quantum Electronics, 2023, 40(5): 759-769.

参考文献

[1] Landaurer, R. (1961). Irreversibility and heat generation in the computational process. IBM Journal of Research and Development, 5, 183-191
[2] Bennett, C. H. (1973). Logical reversibility of computation. Maxwell’s Demon. Entropy, Information, Computing, 197-204.
[3] Perkowski, M., Jozwiak, L., Kerntopf, P., Mishchenko, A., Al-Rabadi, A., Coppola, A., ... & Chrzanowska-Jeske, M. (2001). A general decomposition for reversible logic.
[4] Perkowski, M., & Kerntopf, P. (2001). Reversible logic. Invited tutorial. Proc. EURO-MICRO.
[5] Babu, H. M. H., & Chowdhury, A. R. (2005, January). Design of a reversible binary coded decimal adder by using reversible 4-bit parallel adder. In 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design (pp. 255-260). IEEE.
[6] Nielson, M. A., & Chuang, I. L. (2000). Quantum computation and quantum information.
[7] Satsangi, S., & Patvardhan, C. (2016). Enhanced Quantum Inspired Evolutionary Algorithm for Automatic synthesis of Reversible Circuits.International Journal of Engineering Technology Science and Research, 3(1), 34-45.
[8] Bechmann-Pasquinucci, H., & Peres, A. (2000). Quantum cryptography with 3-state systems. Physical Review Letters, 85(15), 3313.
[9] Bourennane, M., Karlsson, A., & Bj?rk, G. (2001). Quantum key distribution using multilevel encoding. Physical Review A, 64(1), 012306.
[10] Greentree, A. D., Schirmer, S. G., Green, F., Hollenberg, L. C., Hamilton, A. R., & Clark, R. G. (2004). Maximizing the Hilbert space for a finite number of distinguishable quantum states. Physical review letters, 92(9), 097901.
[11] Miller, D. M., & Thornton, M. A. (2007). Multiple valued logic: concepts and representations. Synthesis lectures on digital circuits and systems, 2(1), 1-127.
[12] Curtis, E., & Perkowski, M. (2004). A transformation based algorithm for ternary reversible logic synthesis using universally controlled ternary gates.Proc. IWLS 2004, 345-352.
[13] Zadeh, R. P., & Haghparast, M. (2011). A new reversible/quantum ternary comparator. Australian Journal of Basic and Applied Sciences, 5(12), 2348-2355.
[14] Khan, M. H., Perkowski, M. A., Khan, M. R., & Kerntopf, P. (2005). Ternary GFSOP minimization using kronecker decision diagrams and their synthesis with quantum cascades. Journal of Multiple Valued Logic and Soft Computing, 11(5/6), 567.
[15] Khan, M. H., Perkowski, M. A., & Khan, M. R. (2004, May). Ternary Galois field expansions for reversible logic and Kronecker decision diagrams for ternary GFSOP minimization [Galois field sum of products]. In Multiple-Valued Logic, 2004. Proceedings. 34th International Symposium on (pp. 58-67). IEEE.
[16] Khan, M. H., & Perkowski, M. (2005, September). Quantum realization of ternary encoder and decoder. In Proc. 7th Int. Symp. Representations and Methodology of Future Computing Technologies (RM2005), Tokyo, Japan.
[17] Khan, M. H. (2006). Design of Reversible/Quantum Ternary Multiplexer and Demultiplexer. Engineering letters, 13(2), 65-69.
[18] Monfared, A. T., & Haghparast, M. (2016). Design of New Quantum/Reversible Ternary Subtractor Circuits. Journal of Circuits, Systems and Computers, 25(02), 1650014.
[19] Monfared, A. T., & Haghparast, M. (2015). Novel Design of Quantum/Reversible Ternary Comparator Circuits. Journal of Computational and Theoretical Nanoscience, 12(12), 5670-5673.
[20] Houshmand, P., & Haghparast, M. (2015). Design of a novel quantum reversible ternary up-counter. International Journal of Quantum Information, 13(05), 1550038.
[21] Haghparast, M., Wille, R., & Monfared, A. T. (2017). Towards quantum reversible ternary coded decimal adder. Quantum Information Processing, 16(11), 284.
[22] Monfared, A. T., & Haghparast, M. (2017). Designing new ternary reversible subtractor circuits. Microprocessors and Microsystems, 53, 51-56.
[23] Khan, M. H., & Perkowski, M. A. (2007, May). GF (4) based synthesis of quaternary reversible/quantum logic circuits. In 37th International Symposium on Multiple-Valued Logic (ISMVL'07) (pp. 11-11). IEEE.
[24] Khan, M. H. (2008, May). Reversible realization of quaternary decoder, multiplexer, and demultiplexer circuits. In 38th International Symposium on Multiple Valued Logic (ismvl 2008) (pp. 208-213). IEEE.
[25] ahangir, I., & Das, A. (2010, December). On the design of quaternary comparators. In Computer and Information Technology (ICCIT), 2010 13th International Conference on (pp. 241-246). IEEE.
[26] Khan, M. H. (2008). Synthesis of quaternary reversible/quantum comparators.Journal of Systems Architecture, 54(10), 977-982.
[27] Khan, M. M. M., Biswas, A. K., Chowdhury, S., Tanzid, M., Mohsin, K. M., Hasan, M., & Khan, A. I. (2008, November). Quantum realization of some quaternary circuits. In TENCON (Vol. 2008, pp. 19-21).
[28] Khan, M. H. (2009, May). Scalable Architectures for Design of Reversible Quaternary Multiplexer and Demultiplexer Circuits. In 2009 39th International Symposium on Multiple-Valued Logic (pp. 343-348). IEEE.
[29] Khan, M. H., & Thapliyal, H. (2015, July). Reversible Logic Based Mapping of Quaternary Sequential Circuits Using QGFSOP Expression. In 2015 IEEE Computer Society Annual Symposium on VLSI (pp. 297-302). IEEE.
[30] Meena, J. K., Jain, S. C., Gupta, H., & Gupta, S. (2015, March). Synthesis of balanced quaternary reversible logic circuit. In Circuit, Power and Computing Technologies (ICCPCT), 2015 International Conference on (pp. 1-6). IEEE.
[31] Haghparast, M., & Monfared, A. T. (2017). Designing Novel Quaternary Quantum Reversible Subtractor Circuits. International Journal of Theoretical Physics, 1-12.
[32] Haghparast, M., & Dousttalab, N. (2017). Design of new reversible quaternary flip-flops. International Journal of Quantum Information, 15(04), 1750024.
[33] Haghparast, M., & Monfared, A. T. (2017). Novel Quaternary Quantum Decoder, Multiplexer and Demultiplexer Circuits. International Journal of Theoretical Physics, 56(5), 1694-1707.
[34] Muthukrishnan, A., & Stroud Jr, C. R. (2000). Multivalued logic gates for quantum computation. Physical Review A, 62(5), 052309.
[35] Thapliyal, H. (2016). Mapping of Subtractor and Adder-Subtractor Circuits on Reversible Quantum Gates. In Transactions on Computational Science XXVII (pp. 10-34). Springer Berlin Heidelberg.
[36] Taheri Monfared, A., & Haghparast, M. (2016). Design of novel quantum/reversible ternary adder circuits. International Journal of Electronics Letters, 1-9.
[37] Haghparast, M., & Bolhassani, A. (2016). Optimized parity preserving quantum reversible full adder/subtractor. International Journal of Quantum Information, 1650019.
[38] Bose, A., & Babu, H. M. H. (2015, December). Optimized designs of reversible fault tolerant BCD adder and fault tolerant reversible carry skip BCD adder. In 2015 18th International Conference on Computer and Information Technology (ICCIT) (pp. 202-207). IEEE.
[39] Khan, M. H. (2008). A recursive method for synthesizing quantum/reversible quaternary parallel adder/subtractor with look-ahead carry. Journal of Systems Architecture, 54(12), 1113-1121.
[40] Mandal, S. B., Chakrabarti, A., & Sur-Kolay, S. (2012). A synthesis method for quaternary quantum logic circuits. In Progress in VLSI Design and Test (pp. 270-280). Springer Berlin Heidelberg.
[41] Thapliyal, H., & Ranganathan, N. (2011, March). A new reversible design of bcd adder. In 2011 Design, Automation & Test in Europe (pp. 1-4). IEEE.
[42] Burignat, S., & De Vos, A. (2011, June). Test of a majority-based reversible (quantum) 4 bits ripple-carry adder in adiabatic calculation. In Mixed Design of Integrated Circuits and Systems (MIXDES), 2011 Proceedings of the 18th International Conference (pp. 368-373). IEEE.
[43] Mohammadi, M., Eshghi, M., Haghparast, M., & Bahrololoom, A. (2008). Design and optimization of reversible bcd adder/subtractor circuit for quantum and nanotechnology based systems. World Applied Sciences Journal, 4(6), 787-792.
[44] lvhongjun. Research of the quantum reversible logic circuits with a new compound method[J]. Chinese Journal of Quantum Electronics(量子电子学报), 2010, 27(2): 174-179
[45] Khan, M. H. (2006, December). Quantum realization of quaternary Feynman and Toffoli gates. In 2006 International Conference on Electrical and Computer Engineering (pp. 157-160). IEEE.