量子电子学报 ›› 2020, Vol. 37 ›› Issue (3): 370-377.

• 激光应用 • 上一篇    下一篇

一种基于STM32的星载FPGA在轨重构方法研究及地面验证


赵伟1,2,王煜3,赵欣2,鲁月林2   


  1. 1中国科学技术大学环境科学与光电技术学院, 安徽 合肥 230026; 2中国科学院安徽光学精密机械研究所环境光学与技术重点实验室, 安徽 合肥 230031; 3安徽大学物质科学与信息技术研究院, 安徽 合肥 230601
  • 收稿日期:2019-12-24 修回日期:2020-02-23 出版日期:2020-05-28 发布日期:2020-05-28
  • 通讯作者: 联系方式 E-mail:yuwang@aiofm.ac.cn
  • 作者简介:赵伟(1994-),安徽无为人,研究生,主要从事光学仪器电子电路方面的研究。 E-mail:sazw@mail.ustc.edu.cn
  • 基金资助:
    Supported by National Natural Science Youth Foundation of China(国家自然科学基金, 41705016)

Research on On-orbit Reconfiguration Method of Spaceborne FPGA Based on STM32 and Ground Verification

Zhao Wei1,2, Wang Yu3, Zhao Xin2, Lu Yuelin2   

  1. 1 School of Environmental Science and Optoelectronic Technology,University of Science and Technology of China, Hefei 230026, China; 2 Key Laboratory of Environment Optics and Technology, Anhui Institute of Optics and Fine Mechanics, Chinese Academy of Sciences, Hefei 230031, China; 3 Institute of Physical Science and Information Technology, Anhui University, Hefei 230601, China
  • Received:2019-12-24 Revised:2020-02-23 Published:2020-05-28 Online:2020-05-28

摘要: 为了实现某星载差分吸收光谱仪CCD驱动电路的FPGA在轨重构功能,介绍了一种基于STM32的星载FPGA在轨重构的地面验证方法。分析了实际的重构方案并提出地面实验方案,从硬件设计和软件设计两个方面阐述了地面实验的总体方案。经过实验室测试验证,上位机发送和回读的数据一致,STM32可以模拟JTAG协议实现加载配置数据至FPGA,重构时间可缩短至800 ms。该方法的硬件和软件设计是合理可行的,可以完成对FPGA功能的修改。该方案可为CCD驱动电路的FPGA重构方法提供参考。

关键词: 光电子学, 在轨重构, JTAG协议, 星载FPGA, STM32

Abstract: To realize the FPGA on-orbit reconfiguration function of a CCD drive circuit of a spaceborne differential absorption spectrometer, an MCU-based ground verification method for on-board reconfiguration of an FPGA. The actual reconfiguration scheme is analyzed and a ground experiment scheme is proposed. The overall scheme is described from two aspects of hardware design and software design. Arter the test validation in the laboratory environment, it was found that the data sent and read back by the host computer were consistent and STM32 can simulate the JTAG protocol to load configuration data to the FPGA. Reconfiguration time can be shortened to 800 milliseconds. The design of hardware and software is reasonable and feasible. It can complete the modification of FPGA functions. This solution can provide a reference for the CCD driving circuit FPGA reconfiguration method.

Key words: optoelectronics, on-orbit reconfiguration, JTAG protocol, satellite-borne FPGA, STM32

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